CPU Core Architecture/RTL Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ The Role: As a CPU Core Architecture/RTL Engineer, you will have an outstanding opportunity to craft a functional unit in AMD’s next-generation core. You will work as part of an experienced, skilled, and motivated engineering team with a track record of success. You will help make AMD’s ambitious future CPU roadmap a reality while working in a highly collaborative environment at the cutting edge of technology. The Person: You approach challenges relentlessly with both critical thinking and creativity. You work as part of a team with strong communication and collaboration skills. You have a proven understanding of modern CPU architecture and have ideas and/or drive to make it even better. Does this describe you? If so, then join us! Key Responsibilities: Execute on RTL design and coding for various sections of the processor core pipeline and related logic Collaborate with a team of hardware and software engineers to define the high-level architecture Participate in the definition of microarchitecture of next-generation high-performance processor cores Contribute to design verification, synthesis, power reduction, timing convergence, and floorplan efforts Preferred Experience: Verilog RTL development with industry tools in a CPU, SOC or ASIC environment Demonstrates expertise in the following: Processor architecture, Logic design RTL coding experience for a high-speed processor Power-saving techniques Exposure to physical design and verification methods Awareness of synthesis, place and route, and timing closure concepts Development experience from clean-sheet design to product tapeout to post-silicon debug Proven experience with microarchitecture development, as demonstrated by patents, publications, product features Strong problem-solving and debugging skills Additional Experience Desired: Background in other aspects of ASIC implementation, especially with synthesis flow and static timing analysis Knowledge of microprocessor Design-for-Test (DFT) and Design-for-Debug (DFD) logic and issues Experience in clocking, reset, power-up sequences and power management Experience with x86 or ARM Architecture (ISA) Comfort with scripting such as Perl, Shell and TCL Academic Credentials: Master’s degree preferred with emphasis in Electrical Engineering, Computer Engineering, or Computer Science with a focus on computer architecture. Location: Boxborough, Ma #LI-MR1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. The Role: As a CPU Core Architecture/RTL Engineer, you will have an outstanding opportunity to craft a functional unit in AMD’s next-generation core. You will work as part of an experienced, skilled, and motivated engineering team with a track record of success. You will help make AMD’s ambitious future CPU roadmap a reality while working in a highly collaborative environment at the cutting edge of technology. The Person: You approach challenges relentlessly with both critical thinking and creativity. You work as part of a team with strong communication and collaboration skills. You have a proven understanding of modern CPU architecture and have ideas and/or drive to make it even better. Does this describe you? If so, then join us! Key Responsibilities: Execute on RTL design and coding for various sections of the processor core pipeline and related logic Collaborate with a team of hardware and software engineers to define the high-level architecture Participate in the definition of microarchitecture of next-generation high-performance processor cores Contribute to design verification, synthesis, power reduction, timing convergence, and floorplan efforts Preferred Experience: Verilog RTL development with industry tools in a CPU, SOC or ASIC environment Demonstrates expertise in the following: Processor architecture, Logic design RTL coding experience for a high-speed processor Power-saving techniques Exposure to physical design and verification methods Awareness of synthesis, place and route, and timing closure concepts Development experience from clean-sheet design to product tapeout to post-silicon debug Proven experience with microarchitecture development, as demonstrated by patents, publications, product features Strong problem-solving and debugging skills Additional Experience Desired: Background in other aspects of ASIC implementation, especially with synthesis flow and static timing analysis Knowledge of microprocessor Design-for-Test (DFT) and Design-for-Debug (DFD) logic and issues Experience in clocking, reset, power-up sequences and power management Experience with x86 or ARM Architecture (ISA) Comfort with scripting such as Perl, Shell and TCL Academic Credentials: Master’s degree preferred with emphasis in Electrical Engineering, Computer Engineering, or Computer Science with a focus on computer architecture. Location: Boxborough, Ma #LI-MR1 #LI-Hybrid