Staff Engineer, CPU/RTL
Job Description
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
We’re looking for a CPU Microarchitecture/RTL Engineer to help build high-performance CPUs from scratch. In this role, you’ll own RTL design and microarchitecture, collaborating closely with performance, DV, and physical design teams. You’ll join a deeply technical group delivering performant, power- and timing-optimized RTL for next-gen RISC-V cores.
This role is hybrid, based out of Austin, TX or Santa Clara, CA.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are
- An experienced micro-architect who thrives in building CPU subsystems from scratch.
- Deeply knowledgeable in memory systems miniregand load/store behavior in OoO CPUs.
- A hands-on RTL designer who collaborates cross-functionally to deliver converged logic.
- Excited to experiment, analyze tradeoffs, and iterate to meet performance, power, and area targets.
What We Need
- 5+ years of industry experience with strong CPU RTL and microarchitecture background.
- Proven expertise in Out-of-Order CPU design.
- Experience with Verilog or VHDL, as well as synthesis, timing, and power analysis tools.
- Familiarity with RISC-V, ARM, or x86 ISA architectures and memory consistency models.
- Experience with CHI (Coherent Hub Interface) and/or FUSA (Functional Safety) preferred.
What You Will Learn
- How to design and optimize a custom RISC-V CPU core from first principles.
- How to evaluate and iterate on RTL across performance, timing, and power constraints.
- How a high-performance chip moves from architecture to silicon and post-silicon validation.
- How to contribute to the overall CPU architecture and influence cross-hierarchical tradeoffs.
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government.
Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process.
If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.
