Server HSIO Signal Integrity Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Server HSIO Signal Integrity Lead Engineer   The Role: AMD has an opening for HSIO Signal Integrity lead engineer in Server Division working on system level signal integrity design and customer support for EPYC products. The Person: As a HSIO signal integrity lead engineer on AMD server platform team, you will own simulation methodology, product signal integrity sign off and post si correlation and debugging. you will be directly working together with silicon architecture team, package design team and platform team to influence the design of server products. The main focus will be on system level SI design to meet HSIO interface timing. For post-silicon stage, you will work with electrical validation team for passive and active correlation to build future simulation methodology confidence. Key Responsibilities Lead pathfinding activity for next generation HSIO interface enabling from signal integrity perspective Lead HSIO SI simulation methodology development/improvement Lead sever product system level signal integrity analysis and propose enabling solutions to meet interface timing Collaborate with electrical validation for post silicon correlation Lead SI related post silicon debugging Work closely with the customer support organization to support customers with signal integrity issues Qualifications Deep understanding of industry HSIO protocols like PCIe 4/5/6/7, USB, SATA and Ethernet Deep understanding HSIO system timing allocation and component impact. Deep System-level signal integrity and power integrity understanding including silicon, package, and board. Experience with Electromagnetic modeling of 3-D structures. Candidate must possess a Master's degree in Electrical/Electronic Engineering or equivalent with desired experience in analog/logic validation and characterization. 8+ years of experience with component and system level SIPI analysis Experience with hardware architecture Location: Santa Clara, CA Austin, TX #LI-LM1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. Server HSIO Signal Integrity Lead Engineer   The Role: AMD has an opening for HSIO Signal Integrity lead engineer in Server Division working on system level signal integrity design and customer support for EPYC products. The Person: As a HSIO signal integrity lead engineer on AMD server platform team, you will own simulation methodology, product signal integrity sign off and post si correlation and debugging. you will be directly working together with silicon architecture team, package design team and platform team to influence the design of server products. The main focus will be on system level SI design to meet HSIO interface timing. For post-silicon stage, you will work with electrical validation team for passive and active correlation to build future simulation methodology confidence. Key Responsibilities Lead pathfinding activity for next generation HSIO interface enabling from signal integrity perspective Lead HSIO SI simulation methodology development/improvement Lead sever product system level signal integrity analysis and propose enabling solutions to meet interface timing Collaborate with electrical validation for post silicon correlation Lead SI related post silicon debugging Work closely with the customer support organization to support customers with signal integrity issues Qualifications Deep understanding of industry HSIO protocols like PCIe 4/5/6/7, USB, SATA and Ethernet Deep understanding HSIO system timing allocation and component impact. Deep System-level signal integrity and power integrity understanding including silicon, package, and board. Experience with Electromagnetic modeling of 3-D structures. Candidate must possess a Master's degree in Electrical/Electronic Engineering or equivalent with desired experience in analog/logic validation and characterization. 8+ years of experience with component and system level SIPI analysis Experience with hardware architecture Location: Santa Clara, CA Austin, TX #LI-LM1 #LI-HYBRID