Shift‑Left Physical Design & AI‑Augmented Execution

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. PMTS SILICON DESIGN ENGINEER THE ROLE: We are seeking a senior technical leader to serve as the Chief Engineer ensuring AI‑augmented Physical Design (PD) continues to operate with world‑class engineering rigor. This role sits at the intersection of RTL design, microarchitecture ownership, and Physical Design, with a mandate to shift left PD risk, enforce execution quality, and provide engineering judgment as AI and automation increasingly drive RTL‑to‑GDS flows. THE PERSON: You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: Own Physical Design shift‑left strategy, ensuring PD risks are identified at RTL, SDC, and paper‑floorplan stages Act as chief engineering authority for AI‑assisted and automated PD execution, defining where AI can act autonomously and where human judgment is required Bridge RTL, microarchitecture, and PD, translating early PD findings into architectural and RTL‑level corrective actions Define and enforce PD readiness and quality bars across synthesis, PnR, STA, and physical closure Lead predictive closure and risk management, using early indicators to forecast timing, ECO churn, and execution complexity Govern signoff readiness, ensuring AI‑augmented flows never compromise correctness or confidence Codify execution playbooks and best practices to reduce variability and scale high‑quality PD execution across teams Serve as a trusted technical peer to RTL architects, PD leads, and AI/methodology owners PREFERRED EXPERIENCE: 14–18+ years of semiconductor design experience Strong hands‑on RTL design and microarchitecture ownership, with designs that progressed through PD and tapeout Direct experience working within or closely alongside Physical Design teams Deep understanding of SDC intent, timing, clocking, partitioning, and physical closure trade‑offs Proven ability to resolve PD issues through architectural and RTL‑level solutions, not late physical workarounds Experience driving or contributing to shift‑left initiatives or early physical feasibility analysis Comfort operating as a senior technical authority, making cross‑domain engineering decisions Exposure to AI‑assisted or highly automated design flows is a strong plus Own creation and maintenance of physical‑aware RTL to enable PNR hierarchy, including partitioning, feedthroughs, repeaters, and physical intent insertion. Partner with SOC Design to translate logical IP integration into physical‑aware RTL and with IP design team creation digital‑on‑top RTL wrappers for analog IPs. Must be fluent in physical implementation aspects of functional integration protocols - AXI / APB , NoC , Memory (DDR/HBM) , Coherency, Interrupt/Debug , DFX protocols (iJTAG, BSCAN etc), Clocking and reset logic. ACADEMIC CREDENTIALS: Bachelor’s or Master’s degree in related discipline preferred #LI-AB1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

PMTS SILICON DESIGN ENGINEER THE ROLE: We are seeking a senior technical leader to serve as the Chief Engineer ensuring AI‑augmented Physical Design (PD) continues to operate with world‑class engineering rigor. This role sits at the intersection of RTL design, microarchitecture ownership, and Physical Design, with a mandate to shift left PD risk, enforce execution quality, and provide engineering judgment as AI and automation increasingly drive RTL‑to‑GDS flows. THE PERSON: You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: Own Physical Design shift‑left strategy, ensuring PD risks are identified at RTL, SDC, and paper‑floorplan stages Act as chief engineering authority for AI‑assisted and automated PD execution, defining where AI can act autonomously and where human judgment is required Bridge RTL, microarchitecture, and PD, translating early PD findings into architectural and RTL‑level corrective actions Define and enforce PD readiness and quality bars across synthesis, PnR, STA, and physical closure Lead predictive closure and risk management, using early indicators to forecast timing, ECO churn, and execution complexity Govern signoff readiness, ensuring AI‑augmented flows never compromise correctness or confidence Codify execution playbooks and best practices to reduce variability and scale high‑quality PD execution across teams Serve as a trusted technical peer to RTL architects, PD leads, and AI/methodology owners PREFERRED EXPERIENCE: 14–18+ years of semiconductor design experience Strong hands‑on RTL design and microarchitecture ownership, with designs that progressed through PD and tapeout Direct experience working within or closely alongside Physical Design teams Deep understanding of SDC intent, timing, clocking, partitioning, and physical closure trade‑offs Proven ability to resolve PD issues through architectural and RTL‑level solutions, not late physical workarounds Experience driving or contributing to shift‑left initiatives or early physical feasibility analysis Comfort operating as a senior technical authority, making cross‑domain engineering decisions Exposure to AI‑assisted or highly automated design flows is a strong plus Own creation and maintenance of physical‑aware RTL to enable PNR hierarchy, including partitioning, feedthroughs, repeaters, and physical intent insertion. Partner with SOC Design to translate logical IP integration into physical‑aware RTL and with IP design team creation digital‑on‑top RTL wrappers for analog IPs. Must be fluent in physical implementation aspects of functional integration protocols - AXI / APB , NoC , Memory (DDR/HBM) , Coherency, Interrupt/Debug , DFX protocols (iJTAG, BSCAN etc), Clocking and reset logic. ACADEMIC CREDENTIALS: Bachelor’s or Master’s degree in related discipline preferred #LI-AB1