RTL Integration Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ The Role: As a member of the PCIe design team, you will help bring cutting-edge designs to life. As a member of the IP enablement team, you will work closely with the IP design team, Physical Design teams, and SoC leads to achieve first pass silicon success. The Person: The ideal team member is someone who exhibits a relentless commitment to helping the team meet quality and development goals on schedule. This person is driven to learn and perform at their highest potential in a technical capacity. They thrive in both a team environment and in making individual contributions. Clear and open communication is essential for this role, as they will be involved in meetings, presentations, emails, and reports. A strong team member can learn independently and acquire new skills required for the job. They are also flexible with their working hours to accommodate co-workers in different time-zones. Most importantly, a successful candidate for this role will be a creative innovator and thinker who loves tackling technical problems and enjoys detail-oriented tasks. Key Responsibilities: Integration and Implementation of the AMDs PCI Express (PCIe) subsystem, IP deployment to SoC Synthesis, timing, lint and cdc closure to ensure high quality design. Responsible for implementing design related to tests, debug, clocks Understanding of low power design techniques and having good knowledge of the UPF based power-aware flow Identify complex technical problems, break them down, summarize multiple possible solutions, and lead the team in the right direction Drive and hands-on flow development, automation, and scripting Work collaboratively across teams of IP designers, Physical Design team and SoC level leads Technical and schedule discussion with multi-site engineers and managers Preferred Experience: Understanding of Digital Design in RTL, Verilog HDL Understanding of Synthesis / Linting / CDC tools, equivalence checks Understanding of power saving techniques, including UPF/CPF based power-aware flows and checks Experience with design flows, version control systems, integration and implementation of IPs to SoC. Strong Unix scripting and utilities (Perl/Python/Tcl programming) for analysis and automation Background and working knowledge in ASIC implementation, familiar with Synopsys and Cadence tools Background in clocking, reset, power-up sequences and physical design optimization Academic Credentials: Bachelor/master’s in electrical/computer engineering/engineering science or computer science. #LI-DP1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
The Role: As a member of the PCIe design team, you will help bring cutting-edge designs to life. As a member of the IP enablement team, you will work closely with the IP design team, Physical Design teams, and SoC leads to achieve first pass silicon success. The Person: The ideal team member is someone who exhibits a relentless commitment to helping the team meet quality and development goals on schedule. This person is driven to learn and perform at their highest potential in a technical capacity. They thrive in both a team environment and in making individual contributions. Clear and open communication is essential for this role, as they will be involved in meetings, presentations, emails, and reports. A strong team member can learn independently and acquire new skills required for the job. They are also flexible with their working hours to accommodate co-workers in different time-zones. Most importantly, a successful candidate for this role will be a creative innovator and thinker who loves tackling technical problems and enjoys detail-oriented tasks. Key Responsibilities: Integration and Implementation of the AMDs PCI Express (PCIe) subsystem, IP deployment to SoC Synthesis, timing, lint and cdc closure to ensure high quality design. Responsible for implementing design related to tests, debug, clocks Understanding of low power design techniques and having good knowledge of the UPF based power-aware flow Identify complex technical problems, break them down, summarize multiple possible solutions, and lead the team in the right direction Drive and hands-on flow development, automation, and scripting Work collaboratively across teams of IP designers, Physical Design team and SoC level leads Technical and schedule discussion with multi-site engineers and managers Preferred Experience: Understanding of Digital Design in RTL, Verilog HDL Understanding of Synthesis / Linting / CDC tools, equivalence checks Understanding of power saving techniques, including UPF/CPF based power-aware flows and checks Experience with design flows, version control systems, integration and implementation of IPs to SoC. Strong Unix scripting and utilities (Perl/Python/Tcl programming) for analysis and automation Background and working knowledge in ASIC implementation, familiar with Synopsys and Cadence tools Background in clocking, reset, power-up sequences and physical design optimization Academic Credentials: Bachelor/master’s in electrical/computer engineering/engineering science or computer science. #LI-DP1