AMD
Company
4 months ago
STAFF SILICON LAYOUT ENGINEER
Cork, Ireland
Full-time
Job Description
This job posting has expired and no longer accepting applications.
WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ STAFF SILICON LAYOUT ENGINEER THE ROLE: We are looking for an adaptive, self-motivative custom layout engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The custom layout team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE ROLE: The Serial Transceiver team in AMD designs high speed serial interface systems which are integrated into CPU, GPU and FPGA products. These devices are used in a wide variety of applications involving wireline communications. Successful physical implementation of these serial communications solutions requires an advanced knowledge of mixed signal layout techniques. Successful candidates will work as part of an experienced team executing projects in the latest CMOS FinFET manufacturing processes. Layout is extremely challenging at these smaller process nodes. Project tasks will include layout of analog and digital circuits (some examples of circuits are CTLE, DFE, Multi-GHz PLL design for Rx & Tx serial solutions running up to 200+Gbps); There is also and opportunity to contribute to methodology initiatives to accelerate design layout. Applicants should have experience in some or all of the following areas: Knowledge of advanced layout techniques and hands on experience of layout on advanced nodes(28nm and below) Top level, block level floorplanning. Knowledge of layout effects and best layout practices Ability to understand Design Rules, minimization of parasitic effects, IR drop and Isolation techniques. Experience of Matching / Interdigitation techniques essential. Good problem solving skills Knowledgeable user of industry standard tools including custom layout entry and physical verification Knowledge of Skill programming language a benefit Keen interest in improving layout methodology Experience of Cadence Virtuoso 12.2 or newer preferred. High speed analog circuit layout experience a preference Ability to work independently as well as in teams, including remote design teams Minimum education level/Experience: BS/BEng (Hons) with 10+ years. layout experience #LI-PL1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
STAFF SILICON LAYOUT ENGINEER THE ROLE: We are looking for an adaptive, self-motivative custom layout engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The custom layout team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE ROLE: The Serial Transceiver team in AMD designs high speed serial interface systems which are integrated into CPU, GPU and FPGA products. These devices are used in a wide variety of applications involving wireline communications. Successful physical implementation of these serial communications solutions requires an advanced knowledge of mixed signal layout techniques. Successful candidates will work as part of an experienced team executing projects in the latest CMOS FinFET manufacturing processes. Layout is extremely challenging at these smaller process nodes. Project tasks will include layout of analog and digital circuits (some examples of circuits are CTLE, DFE, Multi-GHz PLL design for Rx & Tx serial solutions running up to 200+Gbps); There is also and opportunity to contribute to methodology initiatives to accelerate design layout. Applicants should have experience in some or all of the following areas: Knowledge of advanced layout techniques and hands on experience of layout on advanced nodes(28nm and below) Top level, block level floorplanning. Knowledge of layout effects and best layout practices Ability to understand Design Rules, minimization of parasitic effects, IR drop and Isolation techniques. Experience of Matching / Interdigitation techniques essential. Good problem solving skills Knowledgeable user of industry standard tools including custom layout entry and physical verification Knowledge of Skill programming language a benefit Keen interest in improving layout methodology Experience of Cadence Virtuoso 12.2 or newer preferred. High speed analog circuit layout experience a preference Ability to work independently as well as in teams, including remote design teams Minimum education level/Experience: BS/BEng (Hons) with 10+ years. layout experience #LI-PL1 #LI-Hybrid
Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
STAFF SILICON LAYOUT ENGINEER THE ROLE: We are looking for an adaptive, self-motivative custom layout engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The custom layout team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE ROLE: The Serial Transceiver team in AMD designs high speed serial interface systems which are integrated into CPU, GPU and FPGA products. These devices are used in a wide variety of applications involving wireline communications. Successful physical implementation of these serial communications solutions requires an advanced knowledge of mixed signal layout techniques. Successful candidates will work as part of an experienced team executing projects in the latest CMOS FinFET manufacturing processes. Layout is extremely challenging at these smaller process nodes. Project tasks will include layout of analog and digital circuits (some examples of circuits are CTLE, DFE, Multi-GHz PLL design for Rx & Tx serial solutions running up to 200+Gbps); There is also and opportunity to contribute to methodology initiatives to accelerate design layout. Applicants should have experience in some or all of the following areas: Knowledge of advanced layout techniques and hands on experience of layout on advanced nodes(28nm and below) Top level, block level floorplanning. Knowledge of layout effects and best layout practices Ability to understand Design Rules, minimization of parasitic effects, IR drop and Isolation techniques. Experience of Matching / Interdigitation techniques essential. Good problem solving skills Knowledgeable user of industry standard tools including custom layout entry and physical verification Knowledge of Skill programming language a benefit Keen interest in improving layout methodology Experience of Cadence Virtuoso 12.2 or newer preferred. High speed analog circuit layout experience a preference Ability to work independently as well as in teams, including remote design teams Minimum education level/Experience: BS/BEng (Hons) with 10+ years. layout experience #LI-PL1 #LI-Hybrid
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AMD
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