SoC Design Verification Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ THE ROLE: As part of the System-On-Chip (SOC) Design Verification team you will be involved in design verification for Design-for-Test/Debug features in complex AMD products. You will have the opportunity to be involved in all stages of the project execution from high level definition and test plan review, through design, verification, and silicon bring-up of those features until deliveries to Platform Debug teams and support during in-lab activities.   THE PERSON: The ideal candidate will report to the SOC Design Verification Manager and thrive in a dynamic team environment. They must have excellent written and verbal communication skills, be a self-starter capable of independently driving tasks to completion, and demonstrate flexibility in taking on various responsibilities. Leadership and mentoring abilities are considered a strong asset. KEY RESPONSIBILITIES: Write and review verification test-plans Develop verification infrastructure, test-bench components, and test-cases Generate and verify test sequences PREFERRED EXPERIENCE: Knowledge of Verilog or SystemVerilog and C/C++ Knowledge of scripting languages, such as Perl or Python, is an advantage Strong analytical/problem solving skills and pronounced attention to details Familiar with entire ASIC design flow, hands on working experience on ASIC DFT/DFD design and verification is an advantage Experience in complex ASIC design (multi-million gates) and in DFT/DFD techniques such as JTAG/IEEE standards, power-gating, on-chip debug logic is an advantage Experience in verification of PHY protocols such as PCIE, XGMI, DDR, HBM, is an advantage ACADEMIC CREDENTIALS: Bachelor’s or master’s degree in computer engineering/electrical engineering #LI-IA1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
THE ROLE: As part of the System-On-Chip (SOC) Design Verification team you will be involved in design verification for Design-for-Test/Debug features in complex AMD products. You will have the opportunity to be involved in all stages of the project execution from high level definition and test plan review, through design, verification, and silicon bring-up of those features until deliveries to Platform Debug teams and support during in-lab activities.   THE PERSON: The ideal candidate will report to the SOC Design Verification Manager and thrive in a dynamic team environment. They must have excellent written and verbal communication skills, be a self-starter capable of independently driving tasks to completion, and demonstrate flexibility in taking on various responsibilities. Leadership and mentoring abilities are considered a strong asset. KEY RESPONSIBILITIES: Write and review verification test-plans Develop verification infrastructure, test-bench components, and test-cases Generate and verify test sequences PREFERRED EXPERIENCE: Knowledge of Verilog or SystemVerilog and C/C++ Knowledge of scripting languages, such as Perl or Python, is an advantage Strong analytical/problem solving skills and pronounced attention to details Familiar with entire ASIC design flow, hands on working experience on ASIC DFT/DFD design and verification is an advantage Experience in complex ASIC design (multi-million gates) and in DFT/DFD techniques such as JTAG/IEEE standards, power-gating, on-chip debug logic is an advantage Experience in verification of PHY protocols such as PCIE, XGMI, DDR, HBM, is an advantage ACADEMIC CREDENTIALS: Bachelor’s or master’s degree in computer engineering/electrical engineering #LI-IA1 #LI-Hybrid