SMTS Silicon Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

SMTS SILICON DESIGN ENGINEER

 

THE ROLE: 

The focus of this role is to plan, build, and execute the design of new and existing features for AMD’s datacenter/automotive IP. 

 

 

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

 

KEY RESPONSIBLITIES:

• Perform Logic design for integration of hard macros, functional units,subsystems, vendor IPs into SoC designs.
• Perform all aspects of the SoC design flow in high-level design, develop and maintain methodology/flows/checks.
• Work closely with Chip Architecture, Design verification, Physical Design, DFT teams to achieve first tapeout success.
• Work with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality
• Participate in silicon bring-up for features owned

 

 

PREFERRED EXPERIENCE:

 

• Have at least 12 years of work experience in ASIC
• Integrating ASIC IP into SOC & block level RTL design.
• Automation using scripting techniques such as PERL, Python or TCL
• Experience in AXI protocol communciation and high-speed interface protocol such as PCIe/Ethernet/DisplayPort/USB
• Experience running quality checks such as Lint and CDC
• Experience with timing constraints generation and UPF methodology
• Experience with simulation/debugging and building block level verification suites
• Experience in synthesis, static timing analysis and ECO
• Design interfacing to PD for floor planning and timing closure
• Excellent verbal and written communication skills, ability to develop clear and concise engineering documentation

 

 

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

 

#LI-SK4

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SMTS SILICON DESIGN ENGINEER

 

THE ROLE: 

The focus of this role is to plan, build, and execute the design of new and existing features for AMD’s datacenter/automotive IP. 

 

 

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

 

KEY RESPONSIBLITIES:

• Perform Logic design for integration of hard macros, functional units,subsystems, vendor IPs into SoC designs.
• Perform all aspects of the SoC design flow in high-level design, develop and maintain methodology/flows/checks.
• Work closely with Chip Architecture, Design verification, Physical Design, DFT teams to achieve first tapeout success.
• Work with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality
• Participate in silicon bring-up for features owned

 

 

PREFERRED EXPERIENCE:

 

• Have at least 12 years of work experience in ASIC
• Integrating ASIC IP into SOC & block level RTL design.
• Automation using scripting techniques such as PERL, Python or TCL
• Experience in AXI protocol communciation and high-speed interface protocol such as PCIe/Ethernet/DisplayPort/USB
• Experience running quality checks such as Lint and CDC
• Experience with timing constraints generation and UPF methodology
• Experience with simulation/debugging and building block level verification suites
• Experience in synthesis, static timing analysis and ECO
• Design interfacing to PD for floor planning and timing closure
• Excellent verbal and written communication skills, ability to develop clear and concise engineering documentation

 

 

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

 

#LI-SK4