Silicon Design Engineer (Design)

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ THE ROLE: Be part of AMD IO IP team, joining IP design work on host controller IP for the next generation of leading-edge super high-speed IO, up to 40 Gb/s. Establishes and maintains AMD's high-speed IO technological leadership position. KEY RESPONSIBILITIES: Takes part in host controller development based on architectural requirements for next-generation IO. Works on STA tasks such as defining clock architecture, creating SDC and exceptions, and analyzing timing reports. Works on RTL code development for IP blocks in Verilog HDL to ensure functionality is correct and reusable for multiple product lines. Deals with complex problems in both STA and RTL. Makes technical decisions. Coaches and mentors junior staff. PREFERRED EXPERIENCE: Expert in Static Timing Analysis, familiar with DC, PT, GCA, and commands, worked in timing closure tasks with high clock frequency. Expert in Verilog RTL design on large-scale digital IP. Specialized knowledge of USB2/3/4 or Thunderbolt specifications is a plus. Specialized knowledge of PCIe or AMBA protocol is a plus. Good English communication, presentation, and documentation. Work is performed with limited supervision. Strong sense of task scheduling and delivering on time as predetermined milestones committed to the manager. Can solve complex, novel, and non-recurring problems. ACADEMIC CREDENTIALS: MS/BS degree of EE or CS, with minimum 7/9 years’ experience. #LI-SH2 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
THE ROLE: Be part of AMD IO IP team, joining IP design work on host controller IP for the next generation of leading-edge super high-speed IO, up to 40 Gb/s. Establishes and maintains AMD's high-speed IO technological leadership position. KEY RESPONSIBILITIES: Takes part in host controller development based on architectural requirements for next-generation IO. Works on STA tasks such as defining clock architecture, creating SDC and exceptions, and analyzing timing reports. Works on RTL code development for IP blocks in Verilog HDL to ensure functionality is correct and reusable for multiple product lines. Deals with complex problems in both STA and RTL. Makes technical decisions. Coaches and mentors junior staff. PREFERRED EXPERIENCE: Expert in Static Timing Analysis, familiar with DC, PT, GCA, and commands, worked in timing closure tasks with high clock frequency. Expert in Verilog RTL design on large-scale digital IP. Specialized knowledge of USB2/3/4 or Thunderbolt specifications is a plus. Specialized knowledge of PCIe or AMBA protocol is a plus. Good English communication, presentation, and documentation. Work is performed with limited supervision. Strong sense of task scheduling and delivering on time as predetermined milestones committed to the manager. Can solve complex, novel, and non-recurring problems. ACADEMIC CREDENTIALS: MS/BS degree of EE or CS, with minimum 7/9 years’ experience. #LI-SH2 #LI-Hybrid