Silicon Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ THE ROLE: Building full-chip RTL connectivity models. Integrating RTL components from multiple design teams. Verifying that full chip models match architectural intent. Developing custom tools and methodologies to improve development efficiency and quality   THE PERSON: We are looking for a RTL digital design engineer to join the FPGA Architecture Development group. The right candidate will focus on full-chip RTL development and integration for next generation FPGA and programmable SoC products. The candidate must be able to work with team members in globally diverse regions. A positive attitude and strong personal desire to "make a difference'. A self-starter who demonstrates an ability to work on own as well within a team. KEY RESPONSIBILITIES: Develop Full Chip SOC RTL Write Full Chip Design Specification document Work with IP development team to integrate IPs Work across architecture, SW and verification teams to assure Full Chip SOC RTL quality Run lint and cdc tools and generate timing constraints PREFERRED EXPERIENCE: Strong experience using FPGAs and understanding FPGA architectures in a semi conductor environment Proven experience with stages in the ASIC design flow including verification methodologies and tools (UVM/OVM, Formal Checks, Lint tools, etc.) Knowledge in RTL and behavioral coding, preferably with Verilog and SystemVerilog Good waveform debug skills using front end industry standard design tools like VCS, NC Sim, or Verdi Knowledge of Unix/Linux environment and scripting languages such as Perl or Python Some Experience using Revision Control tools – CVS, Subversion, or Perforce Presentation Skills ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: San Jose, CA #LI-SC3 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
THE ROLE: Building full-chip RTL connectivity models. Integrating RTL components from multiple design teams. Verifying that full chip models match architectural intent. Developing custom tools and methodologies to improve development efficiency and quality   THE PERSON: We are looking for a RTL digital design engineer to join the FPGA Architecture Development group. The right candidate will focus on full-chip RTL development and integration for next generation FPGA and programmable SoC products. The candidate must be able to work with team members in globally diverse regions. A positive attitude and strong personal desire to "make a difference'. A self-starter who demonstrates an ability to work on own as well within a team. KEY RESPONSIBILITIES: Develop Full Chip SOC RTL Write Full Chip Design Specification document Work with IP development team to integrate IPs Work across architecture, SW and verification teams to assure Full Chip SOC RTL quality Run lint and cdc tools and generate timing constraints PREFERRED EXPERIENCE: Strong experience using FPGAs and understanding FPGA architectures in a semi conductor environment Proven experience with stages in the ASIC design flow including verification methodologies and tools (UVM/OVM, Formal Checks, Lint tools, etc.) Knowledge in RTL and behavioral coding, preferably with Verilog and SystemVerilog Good waveform debug skills using front end industry standard design tools like VCS, NC Sim, or Verdi Knowledge of Unix/Linux environment and scripting languages such as Perl or Python Some Experience using Revision Control tools – CVS, Subversion, or Perforce Presentation Skills ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: San Jose, CA #LI-SC3 #LI-Hybrid