RTL/Integration- Subsystem/IP Design Lead

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We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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SMTS SILICON DESIGN ENGINEER

THE ROLE: 

As a member of the Computing and Graphics group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

RTL/Integration- Design Engineer

The Person:

• If you have an experience developing Subsystem by understanding architectural specification, this role is for you. You will be responsible for making Subsystem work by integrating multiple IPs, performing quality checks and working collaboratively with the IP/SoC team.

Key Responsibilities:

• Design of Subsystems with integration of AMD and other 3rd party IPs

• Perform quality checks (lint, CDC, and power rule checks) of power-gated digital designs
• Work collaboratively with other members of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery to SOC
• Work in partnership with SOC teams to support the IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up
• Lead a subsystem development team of 4 to 5 members.

Preferred Experience:

• 11+ years full-time experience in IP hardware design
• Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs
• Verilog lint tools (Spyglass) and verilog simulation tools (VCS)
• Clock domain crossing (CDC) tools
• Detailed understanding of SoC design flows
• Understanding of IP/SS/SoC Power Management(PM) techniques – Power Gating, Clock Gating
• Experience with embedded processors and data fabric architectures (NoC)
• Outstanding interaction skills while communicating both written and verbally
• Ability to work with multi-level functional teams across various geographies
• Outstanding problem-solving and analytical skills

#LI-NS1

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SMTS SILICON DESIGN ENGINEER

THE ROLE: 

As a member of the Computing and Graphics group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

RTL/Integration- Design Engineer

The Person:

• If you have an experience developing Subsystem by understanding architectural specification, this role is for you. You will be responsible for making Subsystem work by integrating multiple IPs, performing quality checks and working collaboratively with the IP/SoC team.

Key Responsibilities:

• Design of Subsystems with integration of AMD and other 3rd party IPs

• Perform quality checks (lint, CDC, and power rule checks) of power-gated digital designs
• Work collaboratively with other members of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery to SOC
• Work in partnership with SOC teams to support the IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up
• Lead a subsystem development team of 4 to 5 members.

Preferred Experience:

• 11+ years full-time experience in IP hardware design
• Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs
• Verilog lint tools (Spyglass) and verilog simulation tools (VCS)
• Clock domain crossing (CDC) tools
• Detailed understanding of SoC design flows
• Understanding of IP/SS/SoC Power Management(PM) techniques – Power Gating, Clock Gating
• Experience with embedded processors and data fabric architectures (NoC)
• Outstanding interaction skills while communicating both written and verbally
• Ability to work with multi-level functional teams across various geographies
• Outstanding problem-solving and analytical skills

#LI-NS1