MTS Silicon Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

MTS SILICON DESIGN ENGINEER  

 

THE ROLE: 

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s CSoC DV, resulting in no bugs in the final design.   

  

THE PERSON:  

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

 

Key Responsibilities:

• Responsible for participating in the pre-silicon verification for full chip, blocks, multi-chip and system-level verification
• Specifying and owning design verification plan at SOC level/IP level
• Specifying or reviewing verification plans for complex blocks within the ASIC
• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified 
• Responsible for developing complex verification environment using the latest coverage/assertions based verification design methodology, which includes :
  o self-checking, reusable, automated verification environment : both at full-chip & block level
  o Constrained random generators and reference models

Job Requirements and Skills:

• Minimum 8+ years of experience in ASIC Design Verification
• Must have excellent knowledge of ASIC Design Flow and SOC architecture
• Experience in developing complex testbench/model in verilog, System verilog or SystemC
• Experience with coverage-based verification methodology
• Experience in writing testplans and testcases
• Excellent debug skills in functional simulations are must.
• Experience in random test generation, coverage analysis, failure debug
• Experience in low power concepts/verification (NLP/UPF) and emulation is good-to-have
• Strong Verilog, SystemVerilog, PLI interface, C/C++, Python/Perl/shell scripts programming skills.
• Must have good communication skills and the ability/desire to foster a team environment.

 

    

ACADEMIC CREDENTIALS:  

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

 

#LI-PK2

 

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

MTS SILICON DESIGN ENGINEER  

 

THE ROLE: 

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s CSoC DV, resulting in no bugs in the final design.   

  

THE PERSON:  

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

 

Key Responsibilities:

• Responsible for participating in the pre-silicon verification for full chip, blocks, multi-chip and system-level verification
• Specifying and owning design verification plan at SOC level/IP level
• Specifying or reviewing verification plans for complex blocks within the ASIC
• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified 
• Responsible for developing complex verification environment using the latest coverage/assertions based verification design methodology, which includes :
  o self-checking, reusable, automated verification environment : both at full-chip & block level
  o Constrained random generators and reference models

Job Requirements and Skills:

• Minimum 8+ years of experience in ASIC Design Verification
• Must have excellent knowledge of ASIC Design Flow and SOC architecture
• Experience in developing complex testbench/model in verilog, System verilog or SystemC
• Experience with coverage-based verification methodology
• Experience in writing testplans and testcases
• Excellent debug skills in functional simulations are must.
• Experience in random test generation, coverage analysis, failure debug
• Experience in low power concepts/verification (NLP/UPF) and emulation is good-to-have
• Strong Verilog, SystemVerilog, PLI interface, C/C++, Python/Perl/shell scripts programming skills.
• Must have good communication skills and the ability/desire to foster a team environment.

 

    

ACADEMIC CREDENTIALS:  

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

 

#LI-PK2