Hardware Integration Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s embedded division including FPGAs and custom ASICs   THE PERSON:  You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.   KEY RESPONSIBILITIES:  Collaborate with various teams and other design engineers to understand, implement, and verify the existing/new features Perform synthesis and place and route using various flows/tools Validate timing and electrical on new designs and iterate design to drive down violations and close design requirements Oversee LVS/DRC and other physical design verification required to deliver tapeout Integrate numerous blocks and planning chip-level power/bump Plan and drive methodology for upcoming 3DIC products Analyze various design format netlists and general strong debug skills to pinpoint issues Create automation scripts to improve general execution methodology where needed Document and share findings clearly within team as well as outside   PREFERRED EXPERIENCE:  Good understanding of transitor level concepts, exposure to advanced nodes FINFETs a must (16nm, 7nm and beyond) Firm grasp of design concepts such as charge sharing, RC, CR, delay modeling Experienced with industry standard tools including Primetime, Totem, RHSC, Cadence, IC Compiler2 Proficient with synthesis and place and route flows Able to trace/read Verilog, system verilog Experienced with planning for power delivery network (PDN) and chip level integration Proficient with scripting languages including TCL, Python, Perl, C++, etc. Good undestanding of electrical requirements such as ESD, IR drop, Electromigration, Antenna Rules, etc. Exposure to SPICE level simulation (XA, HSPICE, Spectre, etc.) Good understanding of RTL2GDS flow Desirable assets with prior exposure to FPGA a bonus Prior experience with ownership CAD flows/tools a bonus Exposure to 3DIC related skills a bonus   ACADEMIC CREDENTIALS:  Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: San Jose, CA #LI-DW1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s embedded division including FPGAs and custom ASICs   THE PERSON:  You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.   KEY RESPONSIBILITIES:  Collaborate with various teams and other design engineers to understand, implement, and verify the existing/new features Perform synthesis and place and route using various flows/tools Validate timing and electrical on new designs and iterate design to drive down violations and close design requirements Oversee LVS/DRC and other physical design verification required to deliver tapeout Integrate numerous blocks and planning chip-level power/bump Plan and drive methodology for upcoming 3DIC products Analyze various design format netlists and general strong debug skills to pinpoint issues Create automation scripts to improve general execution methodology where needed Document and share findings clearly within team as well as outside   PREFERRED EXPERIENCE:  Good understanding of transitor level concepts, exposure to advanced nodes FINFETs a must (16nm, 7nm and beyond) Firm grasp of design concepts such as charge sharing, RC, CR, delay modeling Experienced with industry standard tools including Primetime, Totem, RHSC, Cadence, IC Compiler2 Proficient with synthesis and place and route flows Able to trace/read Verilog, system verilog Experienced with planning for power delivery network (PDN) and chip level integration Proficient with scripting languages including TCL, Python, Perl, C++, etc. Good undestanding of electrical requirements such as ESD, IR drop, Electromigration, Antenna Rules, etc. Exposure to SPICE level simulation (XA, HSPICE, Spectre, etc.) Good understanding of RTL2GDS flow Desirable assets with prior exposure to FPGA a bonus Prior experience with ownership CAD flows/tools a bonus Exposure to 3DIC related skills a bonus   ACADEMIC CREDENTIALS:  Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: San Jose, CA #LI-DW1 #LI-HYBRID