DFT - PMTS Silicon Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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PMTS SILICON DESIGN ENGINEER  

HE ROLE: 

As a member of the AMD, you will help bring to life cutting-edge designs. As a member of the DFT team, you will work closely with the Architecture, IP design, Physical Design teams, and Product Engineers to achieve first pass silicon success.

THE PERSON:

The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBLITIES:

• DFT Planning and Architecture definition
• Strong understanding on Scan Architecture and Scan features
• Scan insertion and ATPG pattern generation for Stuck at, Transition ATPG, IDDQ Pattern Generation
• GLS, Timing and Power Aware Simulations
• Test coverage and test cost reduction analysis 
• Yield Analysis & Debug for Design root cause & Recovery
• Post Silicon Bring Up: Planning, Co-ordination, and Execution
• DFT Silicon bring up expertise from across tech various nodes
• Extensive Silicon Debug for Phasing closure and production enablement
• Experience of multiple SOC Tape-Outs and Post Silicon Bring-ups

PREFERRED EXPERIENCE:

• Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.) 
• Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX 
• Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design 

ACADEMIC CREDENTIALS:  

• Bachelor’s or master’s degree in Electronics/VLSI/Electrical Engineering 

#LI-NS1

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

PMTS SILICON DESIGN ENGINEER  

HE ROLE: 

As a member of the AMD, you will help bring to life cutting-edge designs. As a member of the DFT team, you will work closely with the Architecture, IP design, Physical Design teams, and Product Engineers to achieve first pass silicon success.

THE PERSON:

The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBLITIES:

• DFT Planning and Architecture definition
• Strong understanding on Scan Architecture and Scan features
• Scan insertion and ATPG pattern generation for Stuck at, Transition ATPG, IDDQ Pattern Generation
• GLS, Timing and Power Aware Simulations
• Test coverage and test cost reduction analysis 
• Yield Analysis & Debug for Design root cause & Recovery
• Post Silicon Bring Up: Planning, Co-ordination, and Execution
• DFT Silicon bring up expertise from across tech various nodes
• Extensive Silicon Debug for Phasing closure and production enablement
• Experience of multiple SOC Tape-Outs and Post Silicon Bring-ups

PREFERRED EXPERIENCE:

• Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.) 
• Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX 
• Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design 

ACADEMIC CREDENTIALS:  

• Bachelor’s or master’s degree in Electronics/VLSI/Electrical Engineering 

#LI-NS1