ASIC Verification Engineer- AI Assisted Workflows

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE The AMD Memory & System IP (MSIP) team is seeking a verification engineer to plan, develop, and execute IP‑level verification for a microprocessor subsystem within a highly integrated SoC environment. This IP includes embedded firmware, so familiarity with RTL design and firmware interactions is valuable. The team leverages AI and LLM-driven workflows for test generation, debug automation, log analysis, and coverage closure. The person in this role will actively use and help evolve these workflows as part of day‑to‑day verification activities. THE PERSON Candidates who excel in this role typically bring strong verification expertise and analytical thinking, along with the ability to drive test planning through coverage closure. They are comfortable working across hardware and firmware boundaries, adopt AI‑ and LLM‑based tools to enhance verification efficiency, and contribute to improving these workflows over time. Successful candidates collaborate effectively with team members in different locations, communicate clearly in both synchronous and asynchronous settings, and apply their experience with processor-based systems—particularly RISC‑V as a plus—to solve complex verification challenges. KEY RESPONSIBILITIES Partner with architects, RTL designers, and firmware engineers to build comprehensive feature-level test plans Develop and maintain UVM-based verification environments Create directed and constrained-random tests Diagnose test failures across testbench, RTL, and firmware boundaries Analyze functional and code coverage and drive closure Reproduce silicon issues in simulation/formal environments Use AI/LLM tools for verification tasks including test generation, debug automation, and log analysis Identify opportunities to expand AI-based workflows and contribute reusable methodologies Support team learning and knowledge sharing (including mentoring when appropriate) PREFERRED EXPERIENCE Experience with IP-level ASIC verification Strong SystemVerilog and UVM expertise Experience with simulation debug and waveform analysis Familiarity with functional coverage, assertions, and constrained-random verification Experience using AI/LLM tools for engineering tasks Knowledge of C/C++ for testbench or firmware debugging Scripting (Python, Perl, Ruby, or shell) Exposure to RTL design, firmware development, formal, or simulation acceleration Ability to manage multiple technical tasks with clear prioritization ACADEMIC CREDENTIALS:  Bachelor’s or master’s degree in computer engineering/Electrical Engineering #LI-DP1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

THE ROLE The AMD Memory & System IP (MSIP) team is seeking a verification engineer to plan, develop, and execute IP‑level verification for a microprocessor subsystem within a highly integrated SoC environment. This IP includes embedded firmware, so familiarity with RTL design and firmware interactions is valuable. The team leverages AI and LLM-driven workflows for test generation, debug automation, log analysis, and coverage closure. The person in this role will actively use and help evolve these workflows as part of day‑to‑day verification activities. THE PERSON Candidates who excel in this role typically bring strong verification expertise and analytical thinking, along with the ability to drive test planning through coverage closure. They are comfortable working across hardware and firmware boundaries, adopt AI‑ and LLM‑based tools to enhance verification efficiency, and contribute to improving these workflows over time. Successful candidates collaborate effectively with team members in different locations, communicate clearly in both synchronous and asynchronous settings, and apply their experience with processor-based systems—particularly RISC‑V as a plus—to solve complex verification challenges. KEY RESPONSIBILITIES Partner with architects, RTL designers, and firmware engineers to build comprehensive feature-level test plans Develop and maintain UVM-based verification environments Create directed and constrained-random tests Diagnose test failures across testbench, RTL, and firmware boundaries Analyze functional and code coverage and drive closure Reproduce silicon issues in simulation/formal environments Use AI/LLM tools for verification tasks including test generation, debug automation, and log analysis Identify opportunities to expand AI-based workflows and contribute reusable methodologies Support team learning and knowledge sharing (including mentoring when appropriate) PREFERRED EXPERIENCE Experience with IP-level ASIC verification Strong SystemVerilog and UVM expertise Experience with simulation debug and waveform analysis Familiarity with functional coverage, assertions, and constrained-random verification Experience using AI/LLM tools for engineering tasks Knowledge of C/C++ for testbench or firmware debugging Scripting (Python, Perl, Ruby, or shell) Exposure to RTL design, firmware development, formal, or simulation acceleration Ability to manage multiple technical tasks with clear prioritization ACADEMIC CREDENTIALS:  Bachelor’s or master’s degree in computer engineering/Electrical Engineering #LI-DP1 #LI-HYBRID