ASIC Design Verification Engineer at AMD

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ASIC Design Verification Engineer



We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_


This is an exciting opportunity to work on Design Verification in multiple industrial protocols (PCIe/Virtualization), AMD proprietary IP blocks environment, AI topologies and super high speed IO interconnects.



A successful candidate will work with architects and senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.



  • Execute a project independently with global teams to achieve pre-defined goals in time
  • Understand logical design architecture and provide the analyzed data to architects for review
  • Improve existing UVM test bench with advanced design verification methodology
  • Bring up new design features
  • Accountable for project delivery.
  • Establishes and maintains AMD's technological leadership position in the AI industries
  • Considered as technical leader across project and departmental boundaries and has a proven track record for sustained innovation.
  • Is responsible for projects or processes of significant strategic or commercial importance and for project/program results
  • Deals with problems requiring cutting edge approaches and champions innovation across the organization
  • Makes technical decisions that have a significant impact on product families, go to market strategies and customer satisfaction
  • Provides consultative direction with management
  • Improve existing test bench to achieve the goals of reusability, configurability, and scalability
  • Elevating current ASIC design verification quality and the simulation efficiency to higher level



  • Rich experience in constructing highly scalability, configurability and reusability DV test bench.
  • Strong working experience in ASIC design/verification related field in IP, Subsystem or SOC level is preferred
  • Writing System Verilog and/or System C models experience for simulation is preferred
  • Strong writing experience in UVM models, checkers and stimulus, constructing UVM register models and applying constrained random methodology in UVM test environment and stimulus is required
  • Compose test plan and validation vectors to ensure functional completeness
  • Experience with design for verification (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)
  • Should be versatile in any one of the high level verification flow such as SV,UVM, C++ etc. as well as knowledge of industry standard tools for verification
  • Should have excellent communication skills (both written and oral)
  • Strong problem solving skills
  • Excellent programming and scripting languages experience in SV, C/C++, Shell, Perl, Python, TLM2.0 is preferred 


  • Bachelors or Masters degree in Computer Engineering/Computer Science/Electrical Engineering 


  • Markham, Ottawa & Vancouver








Benefits offered are described:  AMD benefits at a glance.


AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

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