AMD
Company
AI Silicon Design Engineer
San Jose, California
Job Description
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are looking for an adaptive, self-motivated senior silicon design engineer to join our growing AI team. As a key contributor, you will be a part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading AI technologies to market. The Design Engineering team will further and encourage continuous technical innovation and at the same time facilitate your steady career development. THE PERSON: You have a passion for modern, complex digital architecture and design in general. You are a responsible teammate who has good communication skills and is flexible in collaborating with engineers in different sites/time zones. You have strong analytical and problem-solving skills and are eager to learn and take on new problems. KEY RESPONSIBILITIES: Digital design implementation and micro-architecture RTL coding in Verilog/SystemVerilog Timing closure - timing constraints, synthesis, logic-depth optimization Design area improvements Design flow quality checks - Lint, CDC, RDC, LCP and others Low power design techniques, UPF included Sub-system/IP Integration into SoC Physical Design support Hardware modeling support PREFERRED EXPERIENCE: 3-5 years of working experience in ASIC design Proficiency in Verilog/SystemVerilog RTL Active knowledge of design QC flows Some pipelined high-speed bus protocol - AXI or similar Multi-clock / multi-reset design knowledge Processor design familiarity Low-power design analysis Design tools including Spyglass, Questa CDC, Conformal, VCS, Verdi, DVE Scripting skills - Shell/Tcl/Perl/Python Version control systems such as Perforce, ICManage ACADEMIC CREDENTIALS: Bachelor's or master's degree in computer engineering/Electrical Engineering LOCATION: San Jose, CA This role is not eligible for Visa sponsorship. #LI-SL2 #LI-HYRBID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.
Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.
THE ROLE: We are looking for an adaptive, self-motivated senior silicon design engineer to join our growing AI team. As a key contributor, you will be a part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading AI technologies to market. The Design Engineering team will further and encourage continuous technical innovation and at the same time facilitate your steady career development. THE PERSON: You have a passion for modern, complex digital architecture and design in general. You are a responsible teammate who has good communication skills and is flexible in collaborating with engineers in different sites/time zones. You have strong analytical and problem-solving skills and are eager to learn and take on new problems. KEY RESPONSIBILITIES: Digital design implementation and micro-architecture RTL coding in Verilog/SystemVerilog Timing closure - timing constraints, synthesis, logic-depth optimization Design area improvements Design flow quality checks - Lint, CDC, RDC, LCP and others Low power design techniques, UPF included Sub-system/IP Integration into SoC Physical Design support Hardware modeling support PREFERRED EXPERIENCE: 3-5 years of working experience in ASIC design Proficiency in Verilog/SystemVerilog RTL Active knowledge of design QC flows Some pipelined high-speed bus protocol - AXI or similar Multi-clock / multi-reset design knowledge Processor design familiarity Low-power design analysis Design tools including Spyglass, Questa CDC, Conformal, VCS, Verdi, DVE Scripting skills - Shell/Tcl/Perl/Python Version control systems such as Perforce, ICManage ACADEMIC CREDENTIALS: Bachelor's or master's degree in computer engineering/Electrical Engineering LOCATION: San Jose, CA This role is not eligible for Visa sponsorship. #LI-SL2 #LI-HYRBID
Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.
THE ROLE: We are looking for an adaptive, self-motivated senior silicon design engineer to join our growing AI team. As a key contributor, you will be a part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading AI technologies to market. The Design Engineering team will further and encourage continuous technical innovation and at the same time facilitate your steady career development. THE PERSON: You have a passion for modern, complex digital architecture and design in general. You are a responsible teammate who has good communication skills and is flexible in collaborating with engineers in different sites/time zones. You have strong analytical and problem-solving skills and are eager to learn and take on new problems. KEY RESPONSIBILITIES: Digital design implementation and micro-architecture RTL coding in Verilog/SystemVerilog Timing closure - timing constraints, synthesis, logic-depth optimization Design area improvements Design flow quality checks - Lint, CDC, RDC, LCP and others Low power design techniques, UPF included Sub-system/IP Integration into SoC Physical Design support Hardware modeling support PREFERRED EXPERIENCE: 3-5 years of working experience in ASIC design Proficiency in Verilog/SystemVerilog RTL Active knowledge of design QC flows Some pipelined high-speed bus protocol - AXI or similar Multi-clock / multi-reset design knowledge Processor design familiarity Low-power design analysis Design tools including Spyglass, Questa CDC, Conformal, VCS, Verdi, DVE Scripting skills - Shell/Tcl/Perl/Python Version control systems such as Perforce, ICManage ACADEMIC CREDENTIALS: Bachelor's or master's degree in computer engineering/Electrical Engineering LOCATION: San Jose, CA This role is not eligible for Visa sponsorship. #LI-SL2 #LI-HYRBID
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