AI and ML Power Methodology Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: A senior power lead for power architecture solutions, specializing in areas like microprocessors, GPUs, and machine learning accelerators to optimize power efficiency and performance. This involves creating power management algorithms, developing power models, and collaborating with cross-functional teams to implement and validate power-saving features throughout the design cycle THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBLITIES: Design and development: Understanding of power architecture solutions for complex hardware, such as ML accelerators and GPUs. Workload Optimization: Analyze the power and performance characteristics of AI, Graphics, Battery life WLs, especially specific WLs for NPUs, GPUs, and CPUs. Performance/Watt Optimization: Focus on maximizing performance while staying within strict power and thermal limits, which is critical for both data center and gaming applications. Power Optimization: Developing and optimizing RTL, architectural and power management features Analysis and modeling: Creating power models and scripts for analysis for performance/power trade-offs. Methodology Development: Researching, developing, and deploying methodologies and automated flows (using scripting languages like Python or Perl) to enhance power analysis efficiency. Collaboration: Working with other teams, including RTL, Architecture, Physical Design, Emulation, software, Firmware to ensure power requirements are met across the hardware-software stack. Leadership: Mentoring junior team members and providing technical leadership on complex projects. PREFERRED EXPERIENCE: Extensive industry experience, with a specialization in low-power-processor architectures or power management. Expertise in ASIC/SoC power analysis and optimization techniques Working experience in dynamic and leakage power estimation, analysis, and reduction at various levels (architecture, RTL, circuit design) AI/ML Concepts: Familiarity with machine learning algorithms and their application to power simulation/optimization, as well as an understanding of NPU function and AI workload characteristics. Proficiency in hardware description languages like Verilog or VHDL, and scripting Strong analytical skills and experience with power analysis tools (e.g., PowerArtist, PTPX) Expertise in hardware description languages (Verilog, VHDL), scripting (Python), and simulation/analysis tools Strong analytical and problem-solving skills to tackle complex, multidisciplinary power and performance challenges. Several years of experience in dynamic and leakage power estimation, analysis, and reduction at various levels (architecture, RTL, circuit design) Strong scripting and automation skills, preferably in Python Excellent communication, presentation, and leadership skills to drive projects and collaborate effectively with cross-functional teams. ACADEMIC CREDENTIALS: Master's degree or PhD in a relevant field, such as Electrical or Computer Engineering, is often preferred. LOCATION: Santa Clara, CA #LI-TB2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE: A senior power lead for power architecture solutions, specializing in areas like microprocessors, GPUs, and machine learning accelerators to optimize power efficiency and performance. This involves creating power management algorithms, developing power models, and collaborating with cross-functional teams to implement and validate power-saving features throughout the design cycle THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBLITIES: Design and development: Understanding of power architecture solutions for complex hardware, such as ML accelerators and GPUs. Workload Optimization: Analyze the power and performance characteristics of AI, Graphics, Battery life WLs, especially specific WLs for NPUs, GPUs, and CPUs. Performance/Watt Optimization: Focus on maximizing performance while staying within strict power and thermal limits, which is critical for both data center and gaming applications. Power Optimization: Developing and optimizing RTL, architectural and power management features Analysis and modeling: Creating power models and scripts for analysis for performance/power trade-offs. Methodology Development: Researching, developing, and deploying methodologies and automated flows (using scripting languages like Python or Perl) to enhance power analysis efficiency. Collaboration: Working with other teams, including RTL, Architecture, Physical Design, Emulation, software, Firmware to ensure power requirements are met across the hardware-software stack. Leadership: Mentoring junior team members and providing technical leadership on complex projects. PREFERRED EXPERIENCE: Extensive industry experience, with a specialization in low-power-processor architectures or power management. Expertise in ASIC/SoC power analysis and optimization techniques Working experience in dynamic and leakage power estimation, analysis, and reduction at various levels (architecture, RTL, circuit design) AI/ML Concepts: Familiarity with machine learning algorithms and their application to power simulation/optimization, as well as an understanding of NPU function and AI workload characteristics. Proficiency in hardware description languages like Verilog or VHDL, and scripting Strong analytical skills and experience with power analysis tools (e.g., PowerArtist, PTPX) Expertise in hardware description languages (Verilog, VHDL), scripting (Python), and simulation/analysis tools Strong analytical and problem-solving skills to tackle complex, multidisciplinary power and performance challenges. Several years of experience in dynamic and leakage power estimation, analysis, and reduction at various levels (architecture, RTL, circuit design) Strong scripting and automation skills, preferably in Python Excellent communication, presentation, and leadership skills to drive projects and collaborate effectively with cross-functional teams. ACADEMIC CREDENTIALS: Master's degree or PhD in a relevant field, such as Electrical or Computer Engineering, is often preferred. LOCATION: Santa Clara, CA #LI-TB2